The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as IC technologies are continually progressing to smaller technology nodes, such as a 65 nm technology node, a 45 nm technology node, and below, simply scaling down similar designs used at larger nodes often results in inaccurate or poorly shaped device features. Rounded corners on a device feature that is designed to have right-angle corners may become more pronounced or more critical in the smaller nodes, preventing the device from performing as desired. Other examples of inaccurate or poorly shaped device features include pinching, necking, bridging, dishing, erosion, metal line thickness variations, and other characteristics that affect device performance. Typically, optical proximity correction (OPC) may be performed on a design pattern to help alleviate some of these difficulties before the pattern is created on a mask. However, current OPC techniques may not offer enough fidelity to correct problems in sub-45 nm designs. Improvements in this area are desired.